Field of the Invention
The present invention relates to a gate drive circuit and a display device using the same, and more particularly, to a gate drive circuit capable of improving reliability in a low-temperature environment and a display device using the same.
Discussion of the Related Art
Examples of flat panel displays include a liquid crystal display device (LCD), an organic light emitting diode display (hereinafter, “OLED display”), a plasma display panel (PDP), and an electrophoretic display (EPD) device.
A display device driving circuit comprises a pixel array for displaying an image, a data drive circuit for supplying a data signal to the data lines of the pixel array, a gate drive circuit (or scan drive circuit) for sequentially supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the pixel array, and a timing controller for controlling the data drive circuit and the gate drive circuit.
Each pixel may comprise a thin film transistor (TFT) that supplies the voltage of the data lines to a pixel electrode in response to a gate pulse supplied through the gate lines. The gate pulse swings between a gate-high voltage (VGH) and a gate-low voltage (VGL). The gate-high voltage (VGH) is set higher than a threshold voltage of the pixel TFT, and the gate-low voltage VGL is set lower than the threshold voltage of the pixel TFT. The TFTs of the pixels are turned on in response to the gate-high voltage.
The technology for embedding the gate drive circuit, along with the pixel array, in a display panel is now used. The gate drive circuit embedded in the display panel is known as a “GIP (Gate In Pane)”. The GIP circuit comprises a shift register. The shift register comprises multiple stages connected in cascade. The stages produce an output in response to a start pulse and shift the output in synchronization with a shift clock.
The stages of the shift register each comprise a Q node for charging the gate lines, a QB node for discharging the gate lines, and a switching circuit connected to the Q node and the QB node. The switching circuit charges the Q node in response to the start pulse or the output of the previous stage to raise the voltage of the gate lines, and discharges the QB node in response to the output of the next stage or a reset pulse. The switching circuit comprises TFTs with a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure.
The number of TFTs used for mobile devices such as smartphones is becoming fewer in order to reduce the bezel of the display panel. A fewer number of TFTs may cause floating periods in which no voltage is applied to the Q node and an output node. In these floating periods, the voltages of the Q node and the output node fluctuate with a clock applied through a parasitic capacitance and the output voltages of other stages. Hence, the gate drive circuit of a mobile device may produce an unstable output due to the floating periods.
The TFT's device characteristics may change with a DC gate bias stress or the temperature in the operating environment. The higher the DC voltage applied to the gate of the TFT and the longer the voltage is applied, the greater the DC gate bias stress. The threshold voltage of the TFT may be shifted by the DC gate bias stress, thereby reducing the on current Ion. The shift in the threshold voltage of the TFT may degrade the picture quality and shorten the lifetime of the display device.